1. Field of the Invention
The present invention relates to an off-line test circuit of a semiconductor integrated logic circuit. More particularly, the present invention relates to an off-line circuit of a functional macro circuit such as an ALU(Arithmetic & Logic Unit) or a RAM(Random Access Memory), embedded in the semiconductor integrated logic circuit.
2. Description of Related Art
In conventional semiconductor integrated logic circuits, a functional macro circuit is integrated together with a random logic circuit on the same semiconductor substrate. In the case of testing the functional macro circuit, an off-line test circuit for testing the functional macro circuit independently of the random logic circuit, is generally added in order to reduce the effort for generating the test vector.
Namely, it is possible to bring the semiconductor integrated logic circuit either in a usual operation mode (a mode when the semiconductor integrated logic circuit chip is packaged) or in a test operation mode, by controlling a signal given to an external test mode setting input pin. For example, if a signal "L" is given on the external test mode setting input pin, the circuit is brought into the normal operation mode, and if a signal "H" is given, the circuit is brought into the test operation mode, so that a functional macro circuit can be independently tested.
In the normal operation mode, for example, signals given to external input pins are applied to a random logic circuit, while an output signal of the random logic circuit can be outputted from the external output pin. Furthermore, an output signal of the functional macro circuit is supplied to a random logic circuit through a buffer circuit, and an output signal of the random logic circuit is alternatively inputted to the functional macro circuit through a selection circuit. Thus, the signals are exchanged between the random logic circuit and the functional macro circuit.
In the test operation mode, on the other hand, a signal given to the external input pin is applied through the buffer circuits and through the selection circuit selectively to the functional macro circuit. An output signal of the functional macro circuit is passed through the buffer circuit and selectively outputted from the external output pin through the selection circuit.
As mentioned above, in the test operation mode, the functional macro circuit can be directly tested through the external input pin and the external output pin from the exterior of the semiconductor circuit chip, independently of the random logic circuit, and the external pin used only for the test is only the test mode setting external input pin for receiving a test mode setting signal.
In this way, it is made possible by controlling the test mode setting signal, that in the test operation mode, only a test vector for testing only the functional macro circuit should be considered, and in the normal operation mode, it is not required to consider the testing of the functional macro circuit and it is sufficient if only the test vector for testing only the random logic circuit is considered. Thus, even if the scale of the random logic circuit increases or if the logic becomes more complicate, it is possible to reduce the effort of generating the test vector, because it is not required to test the functional macro circuit through the random logic circuit.
However, in such a conventional example of the semiconductor integrated logic circuit, the functional macro circuit can be directly accessed from the exterior of the semiconductor integrated circuit chip, not through the random logic circuit, by giving a signal to the external input pin in the test operation mode. However, the signal is simultaneously applied to the random logic circuit through the buffer circuits. This may cause an internal circuit of the random logic circuit to operate in the course of the test operation mode.
Further, the output signal of the functional macro circuit is inputted to the random logic circuit through the buffer circuit in the course of the test operation mode. This may also cause the internal circuit of the random logic circuit to operate in the course of the test operation mode.
These factors cause the following problems:
1) The internal condition of the random logic circuit immediately after the test operation mode is completed and the circuit is returned to the normal operation mode, is different from that of the random logic circuit just before the circuit is brought into the test operation mode. PA1 2) In the case that the random logic circuit supplies and receives signals through an external bidirectional pin and also controls a signal for switching the signal inputting/outputting condition of the external bidirectional pin, the signal inputting/outputting condition of this external bidirectional pin cannot be expected in the course of the test operation mode. Consequently, the switching between a driver and a comparator in a LSI (large scaled integrated circuit) tester connected to this bidirectional pin cannot be effected in the course of the test operation mode. Thus, it causes inconsistency between the LSI tester and the signal inputting/outputting condition of the external bidirectional pin of the semiconductor circuit chip, which may destroy the semiconductor circuit chip itself. PA1 3) As a result of an unexpected circuit operation of the random logic circuit in the course of the test operation mode, in the case that a buffer circuit for the output interface connected to the random logic circuit outputs the identical signals simultaneously, a large amount of current may flow in a voltage supply simultaneously. This large amount of current causes noise, so that the voltage level of the voltage supply varies, which affects the test of the functional macro circuit in the test operation mode, namely, it may cause malfunction.
Consequently, if the test operation mode is effected in the course of the normal operation mode, the normal operation mode cannot be tested successively. Thus, it is necessary to initialize the circuit each time the test operation mode is finished, and to test the normal operation mode from the beginning.